Design01.svd

<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
  <name>CY8C5888LTI_LP097</name>
  <version>0.1</version>
  <description>CY8C58LP</description>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <peripherals>
    <peripheral>
      <name>I2C</name>
      <description>No description available</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>I2C_FF_XCFG</name>
          <description>I2C Extended Configuration Register</description>
          <addressOffset>0x400049C8</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>csr_clk_en</name>
              <description>This bit is used for gating system clock for the blocks core logic that is not associated with AHB interface. Clock is made available to the core logic only when this bit is set to 1 and the input pin ext_clk_en is also active. If either of them is not active, the blocks core logic does not receive the system clock.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>i2c_on</name>
              <description>This bit should be set by the user during initial block configuration if the user wants to use the I2C block as wake-up source. Only when this bit set along with other bits mentioned in the sleep mode section, the I2C wakes up system from sleep on address match.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ready_to_sleep</name>
              <description>Once the user sets the force_nack bit, the I2C block sets this bit if I2C is not busy or it waits for ongoing transaction to be completed and then sets this bit. As long as this bit is set, the I2C block is going to nack all the transactions.Clearing force_nack bit automatically clears this bit. HW clears this bit automatically on assertion of PD (Power Down)</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>force_nack</name>
              <description>This bit must be set by the user before putting the device to sleep and wait for ready_to_sleep status bit to be set. This can be cleared by user by writing '0' and the HW clears it automatically on assertion of PD(Power Down)</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>hw_addr_en</name>
              <description>When this bit is set to a '1', hardware address compare is enabled. On an address match, an interrupt is generated, CSR register bit 3 is set, and the clock is stalled until the CPU writes a 0 into the CSR register bit 3. The address is automatically ACKed on a match. On an address mismatch,no interrupt is generated, clock is not stalled, and bit 3 in the CSR register is set. The CPU must write a 0 into the CSR register bit 3 to clear it. The address is automatically NACKed on a mismatch. You must configure the compare address in the ADR register. When this bit is set to a '0', software address compare is enabled. An interrupt is generated, the clock is stalled, and CSR register bit 3 is set when the received address byte is available in the Data register; to enable the CPU to do a firmware address compare. The clock is stalled until the CPU writes a 0 into the CSR register bit 3. The functionality of this bit is independent of the data buffering mode.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF_ADDR</name>
          <description>I2C Slave Adddress Register</description>
          <addressOffset>0x400049CA</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>slave_address</name>
              <description>These seven bits hold the slave's own device address. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF_CFG</name>
          <description>I2C Configuration Register</description>
          <addressOffset>0x400049D6</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>sio_select</name>
              <description>I2C Pin Select for SCL/SDA lines from SIO1/SIO2, 0 = SCL and SDA lines get their inputs from SIO1 module.sclk_str1 and sda_ack1 are driven to SIO1 module and they get asserted once device wakes up from sleep. 1 = SCL and SDA lines get their inputs from SIO2 module. sclk_str2 and sda_ack2 are driven to SIO2 module and they get asserted once device wakes up from sleep. This bit is valid only when I2C.CFG[6] is asserted.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>pselect</name>
              <description>I2C Pin Select for SCL/SDA lines from GPIO/SIO, 0 = SCL and SDA lines get their inputs from GPIO module.sclk_str0 and sda_ack0 are driven to GPIO module and they get asserted once device wakes up from sleep. 1 = SCL and SDA lines get their inputs from one of the SIO Blocks that is chosen based on the configuration of bit I2C.CFG[7]</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>bus_error_ie</name>
              <description>Bus Error Interrupt Enable 0 disabled 1 enabled. An interrupt is generated on the detection of a Bus error condition.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>stop_ie</name>
              <description>Stop Interrupt Enable 0 disabled 1 enabled. An interrupt is generated on the detection of a Stop condition.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>clock_rate</name>
              <description>0 Samples/bit is 16, 1 Samples/bit is 32</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>en_mstr</name>
              <description>Enables master mode for the device</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>en_slave</name>
              <description>Enables Slave mode for the device</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF_CSR</name>
          <description>I2C Control and Status Register</description>
          <addressOffset>0x400049D7</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>bus_error</name>
              <description>It must be cleared by firmware by writing a '0' to the bit position. It is never cleared by the hardware. 1 a misplaced Start or Stop condition was detected. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>lost_arb</name>
              <description>This bit is set immediately on lost arbitration; however, it does not cause an interrupt. This status may be checked after the following Byte Complete interrupt. Any Start detect or a write to the Start or Restart generate bits (MCSR register), when operating in Master mode, will also clear the bit. 1 lost Arbitration. This bit is held zero if I2C_CFG.en_mstr is zero.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>stop_status</name>
              <description>It must be cleared by firmware with write of '0' to the bit position. It is never cleared by the hardware. 1 a Stop condition was detected. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ack</name>
              <description>Acknowledge Out. Bit is automatically cleared by hardware on a Byte Complete event. 0 nack the last received byte. 1 ack the last received byte</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>address</name>
              <description>It must be cleared by firmware with write of '0' to the bit position. 1 the received byte is a slave address. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>transmit</name>
              <description>Bit is set by firmware to define the direction of the byte transfer. Any Start detect will clear the bit. 0 receive mode 1 transmit mode. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>lrb</name>
              <description>Last Received Bit. The value of the 9th bit in a Transmit sequence, which is the acknowledge bit from the receiver. Any Start detect or a write to the Start or Restart generate bits, when operating in Master mode, will also clear the bit. 0 last transmitted byte was ACK'ed by the receiver. 1 last transmitted byte was NACK'ed by the receiver. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>byte_complete</name>
              <description>Transmit/Receive Mode: 0 no completed transmit/receive since last cleared by firmware. Any Start detect or a write to the start or Restart generate bits, when operating in Master mode, will also clear the bit. Transmit mode: 1 eight bits of data have been transmitted and an ACK or NACK has been received. Receive mode: 1 eight bits of data have been received. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF_DATA</name>
          <description>I2C Data Register</description>
          <addressOffset>0x400049D8</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>data</name>
              <description>Read received data or write data to transmit. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF_MCSR</name>
          <description>Master Control and Status Register: I2C_MCSR</description>
          <addressOffset>0x400049D9</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>stop_gen</name>
              <description>This bit is set only for master transmitter and used at the end of byte transfer. After byte complete status is set, if this bit is set followed by the Transmit bit in I2C.CSR register, Stop condition is generated after byte complete. This bit is automatically reset to 0 after the Stop, start or Restart has been generated. During data phase, if Stop Gen bit is set to 0, clearing the Transmit bit in I2C.CSR register will also generate a Stop condition. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>bus_busy</name>
              <description>This bit is set to the following. 0 when a Stop condition is detected (from any bus master). 1 when a Start condition is detected (from any bus master). This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>master_mode</name>
              <description>This bit is set/cleared by hardware when the device is operating as a master. 0 stop condition detected, generated by this device. 1 start condition detected, generated by this device. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>restart_gen</name>
              <description>This bit is cleared by hardware when the Restart generation is complete. 0 restart generation complete. 1 generate a Restart condition. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>start_gen</name>
              <description>This bit is cleared by hardware when the Start generation is complete. 0 start generation complete. 1 generate a Start condition and send a byte (address) to the I2C bus, if bus is not busy. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF_CLK_DIV1</name>
          <description>I2C Clock Divide Factor Register-1</description>
          <addressOffset>0x400049DB</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>Div</name>
              <description>The configuration of this register along with that in register CLK_DIV2 defines the factor by which the SYSCLK will be divided in the I2C block. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF_CLK_DIV2</name>
          <description>I2C Clock Divide Factor Register-2</description>
          <addressOffset>0x400049DC</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>Div</name>
              <description>The configuration of this register along with that in register CLK_DIV1 defines the factor by whichthe SYSCLK will be divided in the I2C block. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF__TMOUT_CSR</name>
          <description>I2C Timerout Control and Status Register</description>
          <addressOffset>0x400049DD</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>sda_pin_status</name>
              <description>SDA Line status.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>scl_pin_status</name>
              <description>SCL Line status.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>i2c_timeout_int_enable</name>
              <description>I2C Timeout interrupt enable.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>i2c_sda_timeout_enable</name>
              <description>I2C SDA Timeout enable.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>i2c_scl_timeout_enable</name>
              <description>I2C SCL Timeout enable.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF__TMOUT_SR</name>
          <description>I2C Timerout Status Register</description>
          <addressOffset>0x400049DE</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>sda_tmout_status</name>
              <description>SDA Timeout status.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>scl_tmout_status</name>
              <description>SCL Timeout status.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF__TMOUT_CFG0</name>
          <description>I2C Timerout Period Configuration Register-0</description>
          <addressOffset>0x400049DF</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>timeout_period_lowbyte</name>
              <description>The configuration of this register along with that in register TMOUT_CFG1 to define the number units before SCL or SDA stuck low timeout triggers the I2C interrupt. The one unit is equal to SYSCLK/1024. The TMOUT_CFG0 defines lower byte of the period.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_FF__TMOUT_CFG1</name>
          <description>Extended Configuration Register: TMOUT_CFG1</description>
          <addressOffset>0x400049E0</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>timeout_period_highnibble</name>
              <description>The configuration of this register along with that in register TMOUT_CFG1 to define the number units before SCL or SDA stuck low timeout triggers the I2C interrupt. The one unit is equal to SYSCLK/1024. The TMOUT_CFG1 defines higher octet of the period.</description>
              <lsb>0</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>UART_1</name>
      <description>UART</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>RX_UART_1_RX_ADDRESS1</name>
          <description>RX Address1 Register</description>
          <addressOffset>0x40006528</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>RX_UART_1_RX_ADDRESS2</name>
          <description>RX Address2 Register</description>
          <addressOffset>0x40006538</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>RX_UART_1_RX_DATA</name>
          <description>RX Data Register</description>
          <addressOffset>0x40006548</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>TX_UART_1_TX_DATA</name>
          <description>TX Data Register</description>
          <addressOffset>0x4000654B</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
        </register>
        <register>
          <name>RX_UART_1_RX_STATUS</name>
          <description>RX status register</description>
          <addressOffset>0x40006569</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>UART_1_RX_STS_MRKSPC</name>
              <description>No description available</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_BREAK</name>
              <description>No description available</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_PAR_ERROR</name>
              <description>No description available</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_STOP_ERROR</name>
              <description>No description available</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_OVERRUN</name>
              <description>No description available</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_FIFO_NOTEMPTY</name>
              <description>No description available</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_RX_STS_ADDR_MATCH</name>
              <description>No description available</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TX_UART_1_TX_STATUS</name>
          <description>TX status register</description>
          <addressOffset>0x4000656B</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>UART_1_TX_STS_COMPLETE</name>
              <description>No description available</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_TX_STS_FIFO_EMPTY</name>
              <description>No description available</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_TX_STS_FIFO_FULL</name>
              <description>No description available</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>UART_1_TX_STS_FIFO_NOT_FULL</name>
              <description>No description available</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>