System Verilog MDR module

• Introduction
• Detailed I/O
• Running on simulation
• Algorithms used

Introduction

Project that contains an arithmetic module that is able to calculates the multiplication, division or square root of signed integers up to 10 bits. Coded in System Verilog.

The module has the following interface:

To see the microarchitecture diagram, please refer to the readme resource.

The module works on simulation using ModelSim and on a physical FPGA DE2-115 board.

Detailed I/O

Each of the I/O ports has a purpose, the table below contains all the detailed description of all the I/O ports of the module:

Name	Category	Description
data	input	Desired number to enter, its format is signed integer. Maximum length n of 10 bits.
start	input	Signal the starts the whole process.
load	input	Signal that indicates a number (data) must be registered.
op	input	Indicates the desired arithmetic operation to execute. M = 0, D = 1 and R = 2.
clk	input	Clock signal.
reset	input	Reset signal.
result	output	Result of the operation (Product, quotient or root), with length of n bits. If there is an overflow, the result will be -1.
remainder	output	Remainder of the operation (only applicable for division and square root).
load x	output	Signal that indicates the module is ready for the data x to be entered. The data y on the multiplication represents the multiplicand, on division is the divisor and on square root is the radicand.
load y	output	Signal that indicates the module is ready for the data y to be entered. The data y on the multiplication represents the multiplier and on division is the dividend (if the operation is square root, this signal is never activated).
error	output	Error signal (division by 0, square root of a negative number).
ready	output	Signal that indicates the module ir ready to perform an operation.

Running on simulation

There are 2 types of simulation: simple and complete. The simple simulation is contained on the tb_simple directory and consists on a simple testbench that tests all 3 arithmetic operations using the same x, y values:

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The complete simulation is contained on the tb_mdr directory and consists on the testbench that test all the possible combinations of the arithmetic operations, by the default the testbench runs with a size n of 10-bit signed integers, so it takes around 30 minutes to execute and validate all 2,098,176 operations.

Running the simple simulation on Modelsim:

cd REPO_PATH/tb_simple;
do run.do

Running the complete simulation on Modelsim:

cd REPO_PATH/tb_mdr;
do run_top.do

Algorithms used

Multiplication algorithm

The Booth's multiplication algorithm was used.

Division algorithm

The Booth's restoring division algorithm was used.

Square root algorithm

The following algorithm was used.