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SDMMC: DMA is disabled too early to complete transfer when reading from SdCard clocked at 16+ MHz from MSI #90
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Hello @dima-kapustin, Thank you for the report. In the meanwhile, I will try to analyze your fix or workaround. With regards. |
Hi @KRASTM ! Here you go (it is almost standard-generated by CubeIDE):
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Hello @dima-kapustin, I tried using the config that you shared, but unfortunately, I didn't manage to reproduce the problem on our board (not the same µc, the L496). In the other hand, I shared your fix and proposal with our team in order to analyze it and confirm it. With regards, |
Hi @KRASTM! Thanks for pushing it through! I am afraid I cannot provide more details about the setup at the moment. We faced the issue when increased SDMMC clock rate over 16 MHz, i.e. 24 MHz and higher. At clock rates lower than or equal to 16 MHz the issue did not appear for years (!). I think there is fundamental issue in the irq processing flow:
However, in the current implementation the cleanup is done after SDMMC reports end of data transmission in both directions - write and read. When SDMMC clock is low enough, everything works fine. But as soon as SDMMC clock rate increases (24+ MHz in our case) the cleanup fails because DMA gets disabled before it completes data transfer and reports end of the transmission. Beat regards, |
Hello @dima-kapustin, There is a section in the datasheet DS11453 page174, about SDMMC characteristics: With regards, |
This is one of the first things we tested... No, it does not help with the issue. Thanks, |
Describe the set-up
Describe the bug
Reading from an SdCard hangs with the following conditions:
SDMMC_DCTRL.DMAEN = 0
SDMMC_DCTRL.DTEN = 0
SDMMC_DCOUNT = 0
DMA_CCR5.EN = 1
DMA_CNDTR5 = 1 (!) which means no transfer complete interrupt will be generated ever
The issue is similar to https://community.st.com/t5/stm32-mcus-products/stm32l4-sd-dma-8-mhz-read-failure-due-to-missing-byte/td-p/385880.
How To Reproduce
SDMMC interface is configured with DMA 2 Channel 5, 1 bit data line
SDMMC clock is sourced form MSI @ 48 MHz, NO devider bypass, HW flow control is ON.
PCLK2 clock is 8.192 MHz and sourced from HSE via PLL
Call HAL_MMC_ReadBlocks_DMA() in a loop to read chunks of 1 or 8 blocks waiting until read completes, i.e. HAL_MMC_GetCardState() returns HAL_MMC_CARD_TRANSFER, after each HAL_MMC_ReadBlocks_DMA() call.
After some successful reads the next reading hangs with the conditions (register values) described above.
HAL driver for SDMMC
(see 1)
(see 1)
Additional context
The root cause is how read completion (SDMMC_STA.DATAEND = 1) is handled in function HAL_MMC_IRQHandler() in stm32l4xx_hal_mmc.c
I did two things in HAL_MMC_IRQHandler() to fix the issue:
As per the reference manual:
-- It is not necessary to clear the enable bit (SDMMC_DCTRL.DTEN) after the end of a data transfer but the SDMMC_DCTRL must be updated to enable a new data transfer
The code in lines 1709-1736 is ALSO present in MMC_DMAReceiveCplt() where it should be executed when DMA reports transfer complete for reads.
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