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This\ndriver currently uses a u32 to store the max possible value\nof the timer. However, statements perform addition of 2 in\nxilinx_pwm_apply() when calculating the period_cycles and\nduty_cycles values. Since priv->max is a u32, this will\nresult in an overflow to 1 which will not only be incorrect\nbut fail on range comparison. This results in making it\nimpossible to set the PWM in this timer mode.\n\nThere are two obvious solutions to the current problem:\n1. Cast each instance where overflow occurs to u64.\n2. Change priv->max from a u32 to a u64.\n\nSolution #1 requires more code modifications, and leaves\nopportunity to introduce similar overflows if other math\nstatements are added in the future. These may also go\nundetected if running in non 32-bit timer modes.\n\nSolution #2 is the much smaller and cleaner approach and\nthus the chosen method in this patch.\n\nThis was tested on a Zynq UltraScale+ with multiple\ninstances of the PWM IP.\n\nSigned-off-by: Ken Sloat \nReviewed-by: Michal Simek \nReviewed-by: Sean Anderson \nLink: https://lore.kernel.org/r/SJ0P222MB0107490C5371B848EF04351CA1E19@SJ0P222MB0107.NAMP222.PROD.OUTLOOK.COM\nSigned-off-by: Michal Simek ","shortMessageHtmlLink":"pwm: xilinx: Fix u32 overflow issue in 32-bit width PWM mode."}},{"before":"2d81f5ef567ce96f29e698939673226d2d1b0fcb","after":"2dc107360e22f09ad50ecf4a4f62b10d78b2cf59","ref":"refs/heads/for-next","pushedAt":"2024-05-02T07:53:27.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"michalsimek","name":"Michal Šimek","path":"/michalsimek","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/4162584?s=80&v=4"},"commit":{"message":"dts: zynqmp: add properties for TCM in remoteproc\n\nAdd properties as per new bindings in zynqmp remoteproc node\nto represent TCM address and size.\n\nThis patch also adds alternative remoteproc node to represent\nremoteproc cluster in split mode. By default lockstep mode is\nenabled and users should disable it before using split mode\ndts. Both device-tree nodes can't be used simultaneously one\nof them must be disabled. For zcu102-1.0 and zcu102-1.1 board\nremoteproc split mode dts node is enabled and lockstep mode\ndts is disabled.\n\nSigned-off-by: Tanmay Shah \nReviewed-by: Mathieu Poirier \nLink: https://lore.kernel.org/r/20240412183708.4036007-4-tanmay.shah@amd.com\nSigned-off-by: Michal Simek ","shortMessageHtmlLink":"dts: zynqmp: add properties for TCM in remoteproc"}},{"before":"d8764d347bd737efec00fae81133ffad0ae084bb","after":"2dc107360e22f09ad50ecf4a4f62b10d78b2cf59","ref":"refs/heads/zynqmp/dt","pushedAt":"2024-05-02T07:52:02.000Z","pushType":"push","commitsCount":10000,"pusher":{"login":"michalsimek","name":"Michal Šimek","path":"/michalsimek","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/4162584?s=80&v=4"},"commit":{"message":"dts: zynqmp: add properties for TCM in remoteproc\n\nAdd properties as per new bindings in zynqmp remoteproc node\nto represent TCM address and size.\n\nThis patch also adds alternative remoteproc node to represent\nremoteproc cluster in split mode. By default lockstep mode is\nenabled and users should disable it before using split mode\ndts. Both device-tree nodes can't be used simultaneously one\nof them must be disabled. For zcu102-1.0 and zcu102-1.1 board\nremoteproc split mode dts node is enabled and lockstep mode\ndts is disabled.\n\nSigned-off-by: Tanmay Shah \nReviewed-by: Mathieu Poirier \nLink: https://lore.kernel.org/r/20240412183708.4036007-4-tanmay.shah@amd.com\nSigned-off-by: Michal Simek ","shortMessageHtmlLink":"dts: zynqmp: add properties for TCM in remoteproc"}},{"before":"90d35da658da8cff0d4ecbb5113f5fac9d00eb72","after":"98369dccd2f8e16bf4c6621053af7aa4821dcf8e","ref":"refs/heads/lkp_test","pushedAt":"2024-04-30T05:43:56.000Z","pushType":"push","commitsCount":10000,"pusher":{"login":"radheyxilinx","name":"Radhey Shyam Pandey","path":"/radheyxilinx","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/6679418?s=80&v=4"},"commit":{"message":"Merge tag 'wq-for-6.9-rc6-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq\n\nPull workqueue fixes from Tejun Heo:\n \"Two doc update patches and the following three fixes:\n\n - On single node systems, the default pool is used but the\n node_nr_active for the default pool was set to min_active. This\n effectively limited the max concurrency of unbound pools on single\n node systems to 8 causing performance regressions on some\n workloads. Fixed by setting the default pool's node_nr_active to\n max_active.\n\n - wq_update_node_max_active() could trigger divide-by-zero if the\n intersection between the allowed CPUs for an unbound workqueue and\n online CPUs becomes empty.\n\n - When kick_pool() was trying to repatriate a worker to a CPU in its\n pod by setting task->wake_cpu, it didn't consider whether the CPU\n being selected is online or not which obviously can lead to\n subobtimal behaviors. On s390, this triggered a crash in arch code.\n The workqueue patch removes the gross misbehavior but doesn't fix\n the crash completely as there's a race window in which CPUs can go\n down after wake_cpu is set. Need to decide whether the fix should\n be on the core or arch side\"\n\n* tag 'wq-for-6.9-rc6-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq:\n workqueue: Fix divide error in wq_update_node_max_active()\n workqueue: The default node_nr_active should have its max set to max_active\n workqueue: Fix selection of wake_cpu in kick_pool()\n docs/zh_CN: core-api: Update translation of workqueue.rst to 6.9-rc1\n Documentation/core-api: Update events_freezable_power references.","shortMessageHtmlLink":"Merge tag 'wq-for-6.9-rc6-fixes' of git://git.kernel.org/pub/scm/linu…"}},{"before":"2de012957c3555b5d1f46cdd63729f43b9bb4514","after":"3af4295e00efdced3e8c6973606a7de55f6bf7dc","ref":"refs/heads/xlnx_rebase_v6.6_LTS","pushedAt":"2024-04-29T05:37:39.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"msreeram-xilinx","name":null,"path":"/msreeram-xilinx","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/60687110?s=80&v=4"},"commit":{"message":"drivers: crypto: xilinx: Add support for do_one_request\n\nAdd support for do_one_request which will be called when the ECDSA\ndriver is probed.\n\nSigned-off-by: Harsha Harsha \nState: pending","shortMessageHtmlLink":"drivers: crypto: xilinx: Add support for do_one_request"}},{"before":"08ceadacc1da15a77045dee6654f9cd906906271","after":"2de012957c3555b5d1f46cdd63729f43b9bb4514","ref":"refs/heads/xlnx_rebase_v6.6_LTS","pushedAt":"2024-04-28T09:07:14.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"msreeram-xilinx","name":null,"path":"/msreeram-xilinx","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/60687110?s=80&v=4"},"commit":{"message":"drivers: crypto: xilinx: Fix the request size\n\nFix the request size to include the size required for fallback cipher.\n\nSigned-off-by: Harsha Harsha \nState: pending","shortMessageHtmlLink":"drivers: crypto: xilinx: Fix the request size"}},{"before":"a33033bade7432af01ed916b9dd7fc6e484d91b9","after":"08ceadacc1da15a77045dee6654f9cd906906271","ref":"refs/heads/xlnx_rebase_v6.6_LTS","pushedAt":"2024-04-26T11:23:52.000Z","pushType":"push","commitsCount":131,"pusher":{"login":"msreeram-xilinx","name":null,"path":"/msreeram-xilinx","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/60687110?s=80&v=4"},"commit":{"message":"phy: xilinx-xhdmiphy: Add support for FRL 6G 3-lane mode\n\nFRL 6G mode works with 3-lane or 4-lane mode. Based on the number of lanes\nretimer chip needs to be configured. Currently driver configures the\nretimer chip always in 4-lane though link is trained with 3-lane\nor 4-lane in 6G FRL mode. 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