emitSystemVerilog in 5.0.0

[kazutomo]

If I run ChiselStage.emitSystemVerilog in 5.0.0, I only see .anno.json file. I'm not sure I'm missing anything or this is a bug. If I specify "-o=filename.v" to firtoolOpts, the specified verilog file is generated (desiredName is ignored).

BTW, here is the import line.
import root.circt.stage.ChiselStage

[kazutomo]

I noticed that emitSystemVerilogFile() correctly generates a verilog file.

[seldridge]

It's expected behavior as emitSystemVerilog is returning a string (and supposed to avoiding all file access). In later versions of Chisel there should be no annotation file, I think, as the annotations are passed in FIRRTL text via a pipe.

Yes, the correct way to do what you want is with the *File* functions which will output a file.

[kazutomo]

Thank you for the insight and for confirming the API!
Since emitVerilog in Chisel 3.x implicitly generates output files (verilog files), I was simply expecting the same behavior.
Although it might be too late, adding an optional argument to emitSystemVerilog for toggling file output could be more user-friendly for those who have migrated from Chisel 3.x, rather than having a separate API (File) for file generation.