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Implement a fixed point 1d convolution that takes a flatten input representation as input and outputs a flatten output representation. This should emulate the input/output shapes on hardware. As the VHDL output of the translate function we have to output some dummy code at first, because the real VHDL implementation is not finished yet. Later on we have to integrate the real VHDL code (see #297).
The text was updated successfully, but these errors were encountered:
Implement a fixed point 1d convolution that takes a flatten input representation as input and outputs a flatten output representation. This should emulate the input/output shapes on hardware. As the VHDL output of the
translate
function we have to output some dummy code at first, because the real VHDL implementation is not finished yet. Later on we have to integrate the real VHDL code (see #297).The text was updated successfully, but these errors were encountered: