make CONFIG=rocket64b1 BOARD=kc705 bitstream encounter error!Also with the other parameter!

[jswxsanta]

env:~20.04.1-Ubuntu SMP Thu Mar 14 14:28:24 UTC 2024 x86_64 x86_64 x86_64 GNU/Linux
and i hve not install vitis because of my computer ram space is not enough.

when run make CONFIG=rocket64b1 BOARD=kc705 bitstream ,Also with the other parameter!

[info] welcome to sbt 1.3.13 (Ubuntu Java 11.0.22)
[info] loading settings for project vivado-risc-v-build from plugins.sbt ...
[info] loading project definition from /root/trunk/vivado-risc-v/project
[info] loading settings for project vivado from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] set current project to vivado (in build file:/root/trunk/vivado-risc-v/)
[info] running freechips.rocketchip.diplomacy.Main --dir /root/trunk/vivado-risc-v/workspace/rocket64b1/system-kc705 --top Vivado.RocketSystem --config Vivado.Rocket64b1
Interrupt map (2 harts 8 interrupts):
[1, 8] => gen

:69.27-72.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property
:94.28-99.5: Warning (simple_bus_reg): /soc/subsystem_pbus_clock: missing or empty reg/ranges property
/dts-v1/;

/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "freechips,rocketchip-vivado-dev";
model = "freechips,rocketchip-vivado";
L15: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;
L4: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
hardware-exec-breakpoint-count = <8>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L10>;
reg = <0x0>;
riscv,isa = "rv64imafdczicsr_zifencei_zihpm_xrocket";
riscv,pmpgranularity = <4>;
riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L2: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L10: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x3 0x80000000>;
};
L14: soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "freechips,rocketchip-vivado-soc", "simple-bus";
ranges;
L6: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L2 3 &L2 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
L7: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
debug-attach = "dmi";
interrupts-extended = <&L2 65535>;
reg = <0x0 0x0 0x0 0x1000>;
reg-names = "control";
};
L1: error-device@3000 {
compatible = "sifive,error0";
reg = <0x0 0x3000 0x0 0x1000>;
};
L9: external-interrupts {
interrupt-parent = <&L5>;
interrupts = <1 2 3 4 5 6 7 8>;
};
L5: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L2 11 &L2 9>;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <8>;
};
L11: mmio-port-axi4@60000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x0 0x60000000 0x20000000>;
};
L12: rom@10000 {
compatible = "sifive,rom0";
reg = <0x0 0x10000 0x0 0x10000>;
reg-names = "mem";
};
L0: subsystem_pbus_clock {
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "subsystem_pbus_clock";
compatible = "fixed-clock";
};
};
};

Generated Address Map
0 - 1000 ARWX debug-controller@0
3000 - 4000 ARWX error-device@3000
10000 - 20000 R X rom@10000
2000000 - 2010000 ARW clint@2000000
c000000 - 10000000 ARW interrupt-controller@c000000
60000000 - 80000000 RWX mmio-port-axi4@60000000
80000000 - 400000000 RWXC memory@80000000

[warn] rocket-chip/src/main/scala/rocket/ICache.scala:500:25: Dynamic index with width 7 is too small for extractee of width 256
[warn] val s1_vb = vb_array(Cat(i.U, s1_idx)) && !s1_slaveValid
[warn] ^
[warn] rocket-chip/src/main/scala/rocket/CSR.scala:959:100: Dynamic index with width 8 is too large for extractee of width 64
[warn] val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_lsbs), read_medeleg(cause_lsbs))
[warn] ^
[warn] rocket-chip/src/main/scala/rocket/CSR.scala:959:126: Dynamic index with width 8 is too large for extractee of width 64
[warn] val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_lsbs), read_medeleg(cause_lsbs))
[warn] ^
[warn] rocket-chip/src/main/scala/rocket/CSR.scala:960:80: Dynamic index with width 8 is too large for extractee of width 64
[warn] val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_lsbs), read_hedeleg(cause_lsbs))
[warn] ^
[warn] rocket-chip/src/main/scala/rocket/CSR.scala:960:106: Dynamic index with width 8 is too large for extractee of width 64
[warn] val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_lsbs), read_hedeleg(cause_lsbs))
[warn] ^
[warn] rocket-chip/src/main/scala/devices/debug/Debug.scala:1727:37: Dynamic index with width 1 is too large for extractee of width 1
[warn] val hartHalted = haltedBitRegs(selectedHartReg)
[warn] ^
[warn] There were 6 warning(s) during hardware elaboration.
[success] Total time: 23 s, completed Apr 17, 2024, 1:04:26 PM
java -Xmx12G -Xss8M -Dsbt.io.virtual=false -Dsbt.server.autostart=false -jar /root/trunk/vivado-risc-v/sbt-launch.jar assembly
[info] welcome to sbt 1.3.13 (Ubuntu Java 11.0.22)
[info] loading settings for project vivado-risc-v-build from plugins.sbt ...
[info] loading project definition from /root/trunk/vivado-risc-v/project
[info] loading settings for project vivado from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] set current project to vivado (in build file:/root/trunk/vivado-risc-v/)
[info] Assembly jar up to date: /root/trunk/vivado-risc-v/target/scala-2.13/system.jar
[success] Total time: 6 s, completed Apr 17, 2024, 1:04:44 PM
rm workspace/bootrom.img
java -Xmx12G -Xss8M -cp realpath target/scala-*/system.jar firrtl.stage.FirrtlMain -i workspace/rocket64b1/system-kc705/RocketSystem.fir -o RocketSystem.v --compiler verilog
--annotation-file workspace/rocket64b1/system-kc705/RocketSystem.anno.json
--custom-transforms firrtl.passes.InlineInstances
--target:fpga
Killed
make: *** [Makefile:264: workspace/rocket64b1/system-kc705.v] Error 137

[jswxsanta]

and the java version is:
openjdk version "11.0.22" 2024-01-16
OpenJDK Runtime Environment (build 11.0.22+7-post-Ubuntu-0ubuntu220.04.1)
OpenJDK 64-Bit Server VM (build 11.0.22+7-post-Ubuntu-0ubuntu220.04.1, mixed mode, sharing)