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Add bytecodes for BSETI, BEXTI, SH1ADD.UW, SH2ADD.UW
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@fwsGonzo
fwsGonzo committed Nov 23, 2023
1 parent 5ac917d commit 4035d90
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Showing 6 changed files with 132 additions and 72 deletions.
171 changes: 101 additions & 70 deletions lib/libriscv/bytecode_impl.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,20 @@ INSTRUCTION(RV32I_BC_ANDI, rv32i_andi) {
REG(fi.get_rs1()) = REG(fi.get_rs2()) & fi.signed_imm();
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_BSETI, rv32i_bseti) {
VIEW_INSTR_AS(fi, FasterItype);
// BSETI: Bit-set immediate
REG(fi.get_rs1()) =
REG(fi.get_rs2()) | (addr_t(1) << fi.unsigned_imm());
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_BEXTI, rv32i_bexti) {
VIEW_INSTR_AS(fi, FasterItype);
// BEXTI: Single-bit Extract
REG(fi.get_rs1()) =
(REG(fi.get_rs2()) >> fi.unsigned_imm()) & 1;
NEXT_INSTR();
}

INSTRUCTION(RV64I_BC_SRLIW, rv64i_srliw) {
if constexpr (W >= 8) {
Expand All @@ -106,18 +120,6 @@ INSTRUCTION(RV64I_BC_SRLIW, rv64i_srliw) {
else UNUSED_FUNCTION();
#endif
}
INSTRUCTION(RV64I_BC_SRAIW, rv64i_sraiw) {
if constexpr (W >= 8) {
VIEW_INSTR_AS(fi, FasterItype);
//dst = (int32_t)src >> instr.Itype.shift_imm();
REG(fi.get_rs1()) =
(int32_t)REG(fi.get_rs2()) >> fi.imm;
NEXT_INSTR();
}
#ifdef DISPATCH_MODE_TAILCALL
else UNUSED_FUNCTION();
#endif
}

#endif // OP_IMM

Expand Down Expand Up @@ -343,10 +345,6 @@ INSTRUCTION(RV32C_BC_STD, rv32c_std) {

#ifdef BYTECODES_OP

INSTRUCTION(RV32I_BC_NOP, rv32i_nop)
{
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_AUIPC, rv32i_auipc)
{
VIEW_INSTR();
Expand Down Expand Up @@ -417,26 +415,6 @@ INSTRUCTION(RV32I_BC_OP_MUL, rv32i_op_mul) {
dst = saddr_t(src1) * saddr_t(src2);
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_DIV, rv32i_op_div) {
OP_INSTR();
// division by zero is not an exception
if (LIKELY(saddr_t(src2) != 0)) {
if constexpr (W == 8) {
// vi_instr.cpp:444:2: runtime error:
// division of -9223372036854775808 by -1 cannot be represented in type 'long'
if (LIKELY(!((int64_t)src1 == INT64_MIN && (int64_t)src2 == -1ll)))
dst = saddr_t(src1) / saddr_t(src2);
} else {
// rv32i_instr.cpp:301:2: runtime error:
// division of -2147483648 by -1 cannot be represented in type 'int'
if (LIKELY(!(src1 == 2147483648 && src2 == 4294967295)))
dst = saddr_t(src1) / saddr_t(src2);
}
} else {
dst = addr_t(-1);
}
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_SH1ADD, rv32i_op_sh1add) {
OP_INSTR();
dst = src2 + (src1 << 1);
Expand Down Expand Up @@ -468,39 +446,6 @@ INSTRUCTION(RV32I_BC_OP_ZEXT_H, rv32i_op_zext_h) {
(void)src2;
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_DIVU, rv32i_op_divu) {
OP_INSTR();
if (LIKELY(src2 != 0)) {
dst = src1 / src2;
} else {
dst = addr_t(-1);
}
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_REM, rv32i_op_rem) {
OP_INSTR();
if (LIKELY(src2 != 0)) {
if constexpr(W == 4) {
if (LIKELY(!(src1 == 2147483648 && src2 == 4294967295)))
dst = saddr_t(src1) % saddr_t(src2);
} else if constexpr (W == 8) {
if (LIKELY(!((int64_t)src1 == INT64_MIN && (int64_t)src2 == -1ll)))
dst = saddr_t(src1) % saddr_t(src2);
} else {
dst = saddr_t(src1) % saddr_t(src2);
}
}
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_REMU, rv32i_op_remu) {
OP_INSTR();
if (LIKELY(src2 != 0)) {
dst = src1 % src2;
} else {
dst = addr_t(-1);
}
NEXT_INSTR();
}

INSTRUCTION(RV64I_BC_OP_ADDW, rv64i_op_addw) {
OP_INSTR();
Expand Down Expand Up @@ -609,6 +554,92 @@ INSTRUCTION(RV32F_BC_FMADD, rv32f_fmadd) {
NEXT_INSTR();
}

#endif // FLP

#ifdef BYTECODES_RARELY_USED

INSTRUCTION(RV64I_BC_SRAIW, rv64i_sraiw) {
if constexpr (W >= 8) {
VIEW_INSTR_AS(fi, FasterItype);
//dst = (int32_t)src >> instr.Itype.shift_imm();
REG(fi.get_rs1()) =
(int32_t)REG(fi.get_rs2()) >> fi.imm;
NEXT_INSTR();
}
#ifdef DISPATCH_MODE_TAILCALL
else UNUSED_FUNCTION();
#endif
}
INSTRUCTION(RV64I_BC_OP_SH1ADD_UW, rv64i_op_sh1add_uw) {
OP_INSTR();
dst = src2 + (addr_t(uint32_t(src1)) << 1);
NEXT_INSTR();
}
INSTRUCTION(RV64I_BC_OP_SH2ADD_UW, rv64i_op_sh2add_uw) {
OP_INSTR();
dst = src2 + (addr_t(uint32_t(src1)) << 2);
NEXT_INSTR();
}

INSTRUCTION(RV32I_BC_OP_DIV, rv32i_op_div) {
OP_INSTR();
// division by zero is not an exception
if (LIKELY(saddr_t(src2) != 0)) {
if constexpr (W == 8) {
// vi_instr.cpp:444:2: runtime error:
// division of -9223372036854775808 by -1 cannot be represented in type 'long'
if (LIKELY(!((int64_t)src1 == INT64_MIN && (int64_t)src2 == -1ll)))
dst = saddr_t(src1) / saddr_t(src2);
} else {
// rv32i_instr.cpp:301:2: runtime error:
// division of -2147483648 by -1 cannot be represented in type 'int'
if (LIKELY(!(src1 == 2147483648 && src2 == 4294967295)))
dst = saddr_t(src1) / saddr_t(src2);
}
} else {
dst = addr_t(-1);
}
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_DIVU, rv32i_op_divu) {
OP_INSTR();
if (LIKELY(src2 != 0)) {
dst = src1 / src2;
} else {
dst = addr_t(-1);
}
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_REM, rv32i_op_rem) {
OP_INSTR();
if (LIKELY(src2 != 0)) {
if constexpr(W == 4) {
if (LIKELY(!(src1 == 2147483648 && src2 == 4294967295)))
dst = saddr_t(src1) % saddr_t(src2);
} else if constexpr (W == 8) {
if (LIKELY(!((int64_t)src1 == INT64_MIN && (int64_t)src2 == -1ll)))
dst = saddr_t(src1) % saddr_t(src2);
} else {
dst = saddr_t(src1) % saddr_t(src2);
}
}
NEXT_INSTR();
}
INSTRUCTION(RV32I_BC_OP_REMU, rv32i_op_remu) {
OP_INSTR();
if (LIKELY(src2 != 0)) {
dst = src1 % src2;
} else {
dst = addr_t(-1);
}
NEXT_INSTR();
}

INSTRUCTION(RV32I_BC_NOP, rv32i_nop)
{
NEXT_INSTR();
}

#ifdef RISCV_EXT_VECTOR
INSTRUCTION(RV32V_BC_VLE32, rv32v_vle32) {
VIEW_INSTR_AS(vi, FasterMove);
Expand All @@ -634,4 +665,4 @@ INSTRUCTION(RV32V_BC_VFADD_VV, rv32v_vfadd_vv) {
}
#endif // RISCV_EXT_VECTOR

#endif // FLP
#endif // BYTECODES_RARELY_USED
9 changes: 9 additions & 0 deletions lib/libriscv/cpu_dispatch.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -136,11 +136,15 @@ void CPU<W>::DISPATCH_FUNC(uint64_t imax)

[RV32I_BC_SEXT_B] = &&rv32i_sext_b,
[RV32I_BC_SEXT_H] = &&rv32i_sext_h,
[RV32I_BC_BSETI] = &&rv32i_bseti,
[RV32I_BC_BEXTI] = &&rv32i_bexti,

[RV64I_BC_ADDIW] = &&rv64i_addiw,
[RV64I_BC_SRLIW] = &&rv64i_srliw,
[RV64I_BC_SRAIW] = &&rv64i_sraiw,
[RV64I_BC_OP_ADDW] = &&rv64i_op_addw,
[RV64I_BC_OP_SH1ADD_UW] = &&rv64i_op_sh1add_uw,
[RV64I_BC_OP_SH2ADD_UW] = &&rv64i_op_sh2add_uw,

#ifdef RISCV_EXT_COMPRESSED
[RV32C_BC_ADDI] = &&rv32c_addi,
Expand Down Expand Up @@ -335,6 +339,7 @@ INSTRUCTION(RV32I_BC_SYSCALL, rv32i_syscall) {

INSTRUCTION(RV32I_BC_FUNCTION, execute_decoded_function) {
VIEW_INSTR();
//printf("Slowpath: 0x%lX\n", pc);
auto handler = decoder->get_handler();
handler(*this, instr);
NEXT_INSTR();
Expand Down Expand Up @@ -398,6 +403,10 @@ INSTRUCTION(RV32I_BC_FUNCBLOCK, execute_function_block) {
NEXT_BLOCK(instr.length());
}

#define BYTECODES_RARELY_USED
# include "bytecode_impl.cpp"
#undef BYTECODES_RARELY_USED

#ifdef DISPATCH_MODE_SWITCH_BASED
default:
goto execute_invalid;
Expand Down
6 changes: 5 additions & 1 deletion lib/libriscv/decode_bytecodes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -261,13 +261,15 @@ size_t CPU<W>::computed_index_for(rv32i_instruction instr)
return RV32I_BC_MV;
else
return RV32I_BC_ADDI;
case 0x1: // SLLI
case 0x1: // SLLI, ...
if (instr.Itype.high_bits() == 0x0)
return RV32I_BC_SLLI;
else if (instr.Itype.imm == 0b011000000100) // SEXT.B
return RV32I_BC_SEXT_B;
else if (instr.Itype.imm == 0b011000000101) // SEXT.H
return RV32I_BC_SEXT_H;
else if (instr.Itype.high_bits() == 0x280) // BSETI
return RV32I_BC_BSETI;
else
return RV32I_BC_FUNCTION;
case 0x2: // SLTI
Expand All @@ -281,6 +283,8 @@ size_t CPU<W>::computed_index_for(rv32i_instruction instr)
return RV32I_BC_SRLI;
else if (instr.Itype.is_srai())
return RV32I_BC_SRAI;
else if (instr.Itype.high_bits() == 0x480) // BEXTI
return RV32I_BC_BEXTI;
else
return RV32I_BC_FUNCTION;
case 0x6:
Expand Down
8 changes: 8 additions & 0 deletions lib/libriscv/tailcall_dispatch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -306,6 +306,10 @@ namespace riscv
cpu.trigger_exception(ILLEGAL_OPCODE, d->instr);
}

#define BYTECODES_RARELY_USED
# include "bytecode_impl.cpp"
#undef BYTECODES_RARELY_USED

namespace
{
template <int W>
Expand Down Expand Up @@ -376,11 +380,15 @@ namespace riscv

[RV32I_BC_SEXT_B] = rv32i_sext_b,
[RV32I_BC_SEXT_H] = rv32i_sext_h,
[RV32I_BC_BSETI] = rv32i_bseti,
[RV32I_BC_BEXTI] = rv32i_bexti,

[RV64I_BC_ADDIW] = rv64i_addiw,
[RV64I_BC_SRLIW] = rv64i_srliw,
[RV64I_BC_SRAIW] = rv64i_sraiw,
[RV64I_BC_OP_ADDW] = rv64i_op_addw,
[RV64I_BC_OP_SH1ADD_UW] = rv64i_op_sh1add_uw,
[RV64I_BC_OP_SH2ADD_UW] = rv64i_op_sh2add_uw,

#ifdef RISCV_EXT_COMPRESSED
[RV32C_BC_ADDI] = rv32c_addi,
Expand Down
4 changes: 4 additions & 0 deletions lib/libriscv/threaded_bytecodes.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -72,11 +72,15 @@ namespace riscv

RV32I_BC_SEXT_B,
RV32I_BC_SEXT_H,
RV32I_BC_BSETI,
RV32I_BC_BEXTI,

RV64I_BC_ADDIW,
RV64I_BC_SRLIW,
RV64I_BC_SRAIW,
RV64I_BC_OP_ADDW,
RV64I_BC_OP_SH1ADD_UW,
RV64I_BC_OP_SH2ADD_UW,

#ifdef RISCV_EXT_COMPRESSED
RV32C_BC_ADDI,
Expand Down
6 changes: 5 additions & 1 deletion lib/libriscv/threaded_rewriter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,9 @@ namespace riscv
}
case RV32I_BC_SLLI:
case RV32I_BC_SRLI:
case RV32I_BC_SRAI: {
case RV32I_BC_SRAI:
case RV32I_BC_BSETI:
case RV32I_BC_BEXTI: {
FasterItype rewritten;
rewritten.rs1 = original.Itype.rd;
rewritten.rs2 = original.Itype.rs1;
Expand Down Expand Up @@ -129,6 +131,8 @@ namespace riscv
case RV32I_BC_OP_REM:
case RV32I_BC_OP_REMU:
case RV64I_BC_OP_ADDW:
case RV64I_BC_OP_SH1ADD_UW:
case RV64I_BC_OP_SH2ADD_UW:
case RV32I_BC_OP_ZEXT_H:
case RV32I_BC_OP_SH1ADD:
case RV32I_BC_OP_SH2ADD:
Expand Down

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