Add bytecodes for SRAIW and ADDW, optimize shift bytecodes

fwsGonzo · Nov 23, 2023 · 5ac917d · 5ac917d
1 parent a49a257
commit 5ac917d
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Showing 6 changed files with 53 additions and 8 deletions.
diff --git a/lib/libriscv/bytecode_impl.cpp b/lib/libriscv/bytecode_impl.cpp
@@ -49,7 +49,7 @@ INSTRUCTION(RV32I_BC_SLLI, rv32i_slli) {
 	VIEW_INSTR_AS(fi, FasterItype);
 	// SLLI: Logical left-shift 5/6/7-bit immediate
 	REG(fi.get_rs1()) =
-		REG(fi.get_rs2()) << (fi.unsigned_imm() & (XLEN - 1));
+		REG(fi.get_rs2()) << fi.unsigned_imm();
 	NEXT_INSTR();
 }
 INSTRUCTION(RV32I_BC_SLTI, rv32i_slti) {
@@ -73,13 +73,13 @@ INSTRUCTION(RV32I_BC_XORI, rv32i_xori) {
 INSTRUCTION(RV32I_BC_SRLI, rv32i_srli) {
 	VIEW_INSTR_AS(fi, FasterItype);
 	// SRLI: Shift-right logical 5/6/7-bit immediate
-	REG(fi.get_rs1()) = REG(fi.get_rs2()) >> (fi.unsigned_imm() & (XLEN - 1));
+	REG(fi.get_rs1()) = REG(fi.get_rs2()) >> fi.unsigned_imm();
 	NEXT_INSTR();
 }
 INSTRUCTION(RV32I_BC_SRAI, rv32i_srai) {
 	VIEW_INSTR_AS(fi, FasterItype);
 	// SRAI: Shift-right arithmetical (preserve the sign bit)
-	REG(fi.get_rs1()) = saddr_t(REG(fi.get_rs2())) >> (fi.unsigned_imm() & (XLEN - 1));
+	REG(fi.get_rs1()) = saddr_t(REG(fi.get_rs2())) >> fi.unsigned_imm();
 	NEXT_INSTR();
 }
 INSTRUCTION(RV32I_BC_ORI, rv32i_ori) {
@@ -99,7 +99,19 @@ INSTRUCTION(RV64I_BC_SRLIW, rv64i_srliw) {
 	if constexpr (W >= 8) {
 		VIEW_INSTR_AS(fi, FasterItype);
 		REG(fi.get_rs1()) = (int32_t)
-			((uint32_t)REG(fi.get_rs2()) >> (fi.imm & 31));
+			((uint32_t)REG(fi.get_rs2()) >> fi.imm);
+		NEXT_INSTR();
+	}
+#ifdef DISPATCH_MODE_TAILCALL
+	else UNUSED_FUNCTION();
+#endif
+}
+INSTRUCTION(RV64I_BC_SRAIW, rv64i_sraiw) {
+	if constexpr (W >= 8) {
+		VIEW_INSTR_AS(fi, FasterItype);
+		//dst = (int32_t)src >> instr.Itype.shift_imm();
+		REG(fi.get_rs1()) =
+			(int32_t)REG(fi.get_rs2()) >> fi.imm;
 		NEXT_INSTR();
 	}
 #ifdef DISPATCH_MODE_TAILCALL
@@ -490,6 +502,12 @@ INSTRUCTION(RV32I_BC_OP_REMU, rv32i_op_remu) {
 	NEXT_INSTR();
 }
 
+INSTRUCTION(RV64I_BC_OP_ADDW, rv64i_op_addw) {
+	OP_INSTR();
+	dst = int32_t(uint32_t(src1) + uint32_t(src2));
+	NEXT_INSTR();
+}
+
 INSTRUCTION(RV32I_BC_SEXT_B, rv32i_sext_b) {
 	VIEW_INSTR_AS(fi, FasterItype);
 	REG(fi.get_rs1()) = saddr_t(int8_t(REG(fi.get_rs2())));

diff --git a/lib/libriscv/cpu_dispatch.cpp b/lib/libriscv/cpu_dispatch.cpp
@@ -139,6 +139,8 @@ void CPU<W>::DISPATCH_FUNC(uint64_t imax)
 
 		[RV64I_BC_ADDIW]  = &&rv64i_addiw,
 		[RV64I_BC_SRLIW]  = &&rv64i_srliw,
+		[RV64I_BC_SRAIW]  = &&rv64i_sraiw,
+		[RV64I_BC_OP_ADDW] = &&rv64i_op_addw,
 
 #ifdef RISCV_EXT_COMPRESSED
 		[RV32C_BC_ADDI]     = &&rv32c_addi,

diff --git a/lib/libriscv/decode_bytecodes.cpp b/lib/libriscv/decode_bytecodes.cpp
@@ -352,6 +352,8 @@ size_t CPU<W>::computed_index_for(rv32i_instruction instr)
 		case RV64I_OP32:
 			switch (instr.Rtype.jumptable_friendly_op())
 			{
+			case 0x0: // ADD.W
+				return RV64I_BC_OP_ADDW;
 			case 0x40: // ADD.UW
 				return RV32I_BC_OP_ADD_UW;
 			case 0x44: // ZEXT.H

diff --git a/lib/libriscv/tailcall_dispatch.cpp b/lib/libriscv/tailcall_dispatch.cpp
@@ -379,6 +379,8 @@ namespace riscv
 
 		[RV64I_BC_ADDIW]  = rv64i_addiw,
 		[RV64I_BC_SRLIW]  = rv64i_srliw,
+		[RV64I_BC_SRAIW]  = rv64i_sraiw,
+		[RV64I_BC_OP_ADDW] = rv64i_op_addw,
 
 #ifdef RISCV_EXT_COMPRESSED
 		[RV32C_BC_ADDI]     = rv32c_addi,

diff --git a/lib/libriscv/threaded_bytecodes.hpp b/lib/libriscv/threaded_bytecodes.hpp
@@ -75,6 +75,8 @@ namespace riscv
 
 		RV64I_BC_ADDIW,
 		RV64I_BC_SRLIW,
+		RV64I_BC_SRAIW,
+		RV64I_BC_OP_ADDW,
 
 #ifdef RISCV_EXT_COMPRESSED
 		RV32C_BC_ADDI,

diff --git a/lib/libriscv/threaded_rewriter.cpp b/lib/libriscv/threaded_rewriter.cpp
@@ -15,6 +15,7 @@ namespace riscv
 		size_t bytecode, [[maybe_unused]] address_t pc, rv32i_instruction& instr)
 	{
 		static constexpr unsigned PCAL = compressed_enabled ? 2 : 4;
+		static constexpr unsigned XLEN = 8 * W;
 		const auto original = instr;
 
 		switch (bytecode)
@@ -35,17 +36,34 @@ namespace riscv
 				instr.whole = rewritten.whole;
 				return bytecode;
 			}
-			case RV64I_BC_ADDIW:
 			case RV64I_BC_SRLIW:
+			case RV64I_BC_SRAIW: {
+				FasterItype rewritten;
+				rewritten.rs1 = original.Itype.rd;
+				rewritten.rs2 = original.Itype.rs1;
+				rewritten.imm = original.Itype.imm & 31;
+
+				instr.whole = rewritten.whole;
+				return bytecode;
+			}
+			case RV32I_BC_SLLI:
+			case RV32I_BC_SRLI:
+			case RV32I_BC_SRAI: {
+				FasterItype rewritten;
+				rewritten.rs1 = original.Itype.rd;
+				rewritten.rs2 = original.Itype.rs1;
+				rewritten.imm = original.Itype.imm & (XLEN-1);
+
+				instr.whole = rewritten.whole;
+				return bytecode;
+			}
+			case RV64I_BC_ADDIW:
 			case RV32I_BC_SEXT_B:
 			case RV32I_BC_SEXT_H:
 			case RV32I_BC_ADDI:
-			case RV32I_BC_SLLI:
 			case RV32I_BC_SLTI:
 			case RV32I_BC_SLTIU:
 			case RV32I_BC_XORI:
-			case RV32I_BC_SRLI:
-			case RV32I_BC_SRAI:
 			case RV32I_BC_ORI:
 			case RV32I_BC_ANDI: {
 				FasterItype rewritten;
@@ -110,6 +128,7 @@ namespace riscv
 			case RV32I_BC_OP_DIVU:
 			case RV32I_BC_OP_REM:
 			case RV32I_BC_OP_REMU:
+			case RV64I_BC_OP_ADDW:
 			case RV32I_BC_OP_ZEXT_H:
 			case RV32I_BC_OP_SH1ADD:
 			case RV32I_BC_OP_SH2ADD: