Add experimental inaccurate dispatch

emulator/src/main.cpp

@@ -303,7 +303,10 @@ static void run_program(
 			debug.simulate();
 		} else {
 			// Normal RISC-V simulation
-			machine.simulate(cli_args.fuel);
+			if (cli_args.accurate)
+				machine.simulate(cli_args.fuel);
+			else
+				machine.cpu.simulate_inaccurate(machine.cpu.pc());
 		}
 	} catch (riscv::MachineException& me) {
 		printf("%s\n", machine.cpu.current_instruction_to_string().c_str());
@@ -342,7 +345,7 @@ static void run_program(
 		const auto retval = machine.return_value();
 		printf(">>> Program exited, exit code = %" PRId64 " (0x%" PRIX64 ")\n",
 			int64_t(retval), uint64_t(retval));
-		if (cli_args.accurate || !riscv::binary_translation_enabled)
+		if (cli_args.accurate)
 		printf("Instructions executed: %" PRIu64 "  Runtime: %.3fms  Insn/s: %.0fmi/s\n",
 			machine.instruction_counter(), runtime.count()*1000.0,
 			machine.instruction_counter() / (runtime.count() * 1e6));

lib/libriscv/bytecode_dispatch.cpp

@@ -8,6 +8,8 @@
 
 #include "cpu_dispatch.cpp"
 
+#include "cpu_inaccurate_dispatch.cpp"
+
 namespace riscv
 {
 	INSTANTIATE_32_IF_ENABLED(CPU);

lib/libriscv/cpu.hpp

@@ -35,6 +35,12 @@ namespace riscv
 		/// @return Returns true if the machine stopped normally, otherwise an execution timeout happened.
 		bool simulate(address_t pc, uint64_t icounter, uint64_t maxcounter);
 
+		/// @brief Simulate faster by not counting instructions, and consequently
+		/// not checking for timeouts. This is useful when there is another
+		/// layer of timeout checking, like signal handling.
+		/// @param pc The starting address
+		void simulate_inaccurate(address_t pc);
+
 		// Step precisely one instruction forward from current PC.
 		void step_one();