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Extended configurability #1170
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Afternoon @LarsAsplund I am currently away from a computer for the next three weeks, but I can answer some of these questions.
Regards, --Jeremy |
I'll respond here since I am the "active" user of this here at the moment.
Appreciate it! :)
We have that one enabled, it doesn't seem to fix the colon around the signal keyword when used in hierarchical references.
We have that rule enabled, with |
Morning @ru551n ,
I reviewed the rule and it should work with hierarchical references. Could you post the output of the following command: vsg -rc signal_006
Maybe I misunderstood the original question. Is the issue the indenting is not working or the structure of the expression (adding or removing carriage returns) the issue? --Jeremy |
|
Afternoon @ru551n , It appears the rule is configured correctly for a single space. I will need to get to a computer before I can debug any further. I will be back from vacation on June 2nd and will take a look at these issues shortly after. Regards --Jeremy |
Morning @ru551n , I have added two new rules to enforce whitespace before port map and generic map assigment operators to branch For the second issue, I have the following code snippet: 1 architecture rtl of fifo is
2
3 signal dut.foo : std_logic;
4
5 begin
6
7 end architecture rtl; I used the following configuration file: 1 "rule": {
2 "global": {
3 "disable" : true
4 },
5 "signal_006": {
6 "disable" : false,
7 "number_of_spaces" : 1
8 }
9 } when I run vsg against the file using the configuration I get the following code: 1 architecture rtl of fifo is
2
3 signal dut.foo : std_logic;
4
5 begin
6
7 end architecture rtl; I must be missing something as rule Regards, --Jeremy |
Afternoon @ru551n , Is there a chance you could post a snippet of the third issue? I have my test example and it seems to be working as expected: 1 architecture rtl of fifo is
2
3 signal dut.foo : std_logic;
4
5 begin
6
7 PROC_1:process
8
9 begin
10
11 if condition_a and condition_b then
12 elsif condition_a and
13 condition_b then
14 end if;
15
16 end process PROC_1;
17
18 end architecture rtl; with this configuration: 1 "rule": {
2 "signal_006": {
3 "disable" : false,
4 "number_of_spaces" : 1
5 },
6 "if_002": {
7 "parenthesis": "remove"
8 },
9 "if_009": {
10 "align_left": true,
11 "align_paren": false
12 }
13 } yields: 1 architecture rtl of fifo is
2
3 signal dut.foo : std_logic;
4
5 begin
6
7 proc_1 : process is
8 begin
9
10 if condition_a and condition_b then
11 elsif condition_a and
12 condition_b then
13 end if;
14
15 end process proc_1;
16
17 end architecture rtl; I feel I am missing something on the last issue. --Jeremy |
Morning @ru551n and @LarsAsplund , Just wanted to ping you on this issue to see if we can move this forward. Thanks, --Jeremy |
Due to some more urgent stuff being requested this has been on hold for a while. Now I am back on it though, so here goes:
alias test is << signal dut.test : std_logic >>; Does not get aligned. |
Evening @LarsAsplund , So apparently it took me awhile to figure out you were referring to Also, would you like similar rules for Regards, --Jeremy |
Works nicely! Regarding external constants and variables, it's not something we use commonly, but if it is not too much work it is better to have than not. Thank you! -- Sebastian |
@jeremiah-c-leary It works perfectly on external names when used with aliases but not on external names used in a context like this:
We use both styles |
Morning @LarsAsplund ,
I can add those rules.
I checked the 2008 LRM and the only definition for an external names are the following:
The Regards, --Jeremy |
Evening @LarsAsplund , I added rules for the Regards, --Jeremy |
I'm introducing vsg in a project which has a history of mixed styles. Some have used alignment, some have not. Moving forward, we will remove all alignment and use
--fix
to enforce that in git hooks. While doing that, we found the following issues (in order of priority):--fix
, we managed to remove spaces after=>
in port and generic mappings but not spaces before=>
. This means that these lines are only partly "de-aligned" after--fix
. For example,my_port => some_signal,
.<< signal dut.foo : signal >>
, we have not been able to remove the spaces before:
.The text was updated successfully, but these errors were encountered: