use fork from Z80core from jitpack.

kopavel · Jun 21, 2024 · f9c96e9 · f9c96e9
1 parent 3b44e10
commit f9c96e9
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Showing 9 changed files with 28 additions and 3,876 deletions.
diff --git a/gradle/versions.toml b/gradle/versions.toml
@@ -12,7 +12,7 @@ junit-launcher = { module = 'org.junit.platform:junit-platform-launcher' }
 idea-gui = 'com.jetbrains.intellij.java:java-gui-forms-rt:+'
 swing-flatlaf = 'com.formdev:flatlaf:3.4.1'
 lombok = { module = 'org.projectlombok:lombok', version.ref = 'lombok' }
-z80 = 'com.codingrodent.microprocessor:Z80Processor:4.2.0'
+z80 = 'com.github.kopavel:Z80Processor:async_IO'
 jackson-databind = { module = 'com.fasterxml.jackson.core:jackson-databind', version.ref = 'jackson' }
 jackson-jakarta-annotations = { module = 'com.fasterxml.jackson.module:jackson-module-jakarta-xmlbind-annotations', version.ref = 'jackson' }
 jackson-dataformat-xml = { module = 'com.fasterxml.jackson.dataformat:jackson-dataformat-xml', version.ref = 'jackson' }

diff --git a/schemaParts/z80/README.md b/schemaParts/z80/README.md
@@ -13,7 +13,7 @@ Implement Zilog Z80 CPU pin and timing level functionality.
 
 **Output names**:
 
-- Ax, where x is number in [0-15] range
+- Ax, where x is numbered in [0-15] range
 - ~{RD}
 - ~{WR}
 - ~{MREQ}
@@ -25,24 +25,21 @@ Implement Zilog Z80 CPU pin and timing level functionality.
 
 **Bidirectional names**:
 
-- Dx, where x is number in [0-7] range
+- Dx, where x is numbered in [0-7] range
 
-Schema part doesn't have any additional parameters.
+The Schema part doesn't have any additional parameters.
 
 <hr>
 
-This component serves as a pin-level wrapper that emulates the behavior of the Z80 processor at the hardware level. It based on
-the [Z80Processor](https://github.com/codesqueak/Z80Processor) project for the CPU core emulation.
-
-The core reimplemented in IoQueue/callback manner for possibility postpone IO request in time for processing hardware layer.
-
+This component serves as a pin-level wrapper that emulates the behavior of the Z80 processor at the hardware level.  
+It is based on [fork](https://github.com/kopavel/Z80Processor) from [Z80Processor](https://github.com/codesqueak/Z80Processor) project for the CPU core emulation.
+The core reimplemented in IoQueue/callback manner for possibility postpone IO request in time for processing hardware layer.  
 The emulation accurately represents the timing diagram of the Z80 processor, with the following exceptions:
 
 - M1 always has 4 T states (plus any additional wait states).
-- Subsequent M states have 3 T states each (plus any additional wait states).
+- Later M states have 3 T states each (plus any additional wait states).
 - IO reads have 3 T states and, as per Z80 specification, one extra Mw state, resulting in a total of 4 states (plus any additional wait states).
 
 Certain functionalities such as NMI, BUSRQ, BUSACK, and refresh activity are currently absent but are planned for future implementation.
-
 Z80Processor contains information about the real T state amount per OPCODE, allowing for precise execution in terms of T states, although this feature is yet to be
 implemented.
diff --git a/...ulator/components/Z80/core/IoRequest.java → schemaParts/z80/build.gradle b/...ulator/components/Z80/core/IoRequest.java → schemaParts/z80/build.gradle
@@ -29,26 +29,14 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
-package lv.pko.KiCadLogicalSchemeSimulator.components.Z80.core;
-import java.util.function.Consumer;
 
-public class IoRequest {
-    public final int address;
-    public final boolean isMemory;
-    public boolean isWrite;
-    public int payload;
-    public Consumer<Integer> callback;
 
-    public IoRequest(int address, int payload, boolean isMemory) {
-        this.address = address;
-        this.payload = payload;
-        this.isMemory = isMemory;
-        isWrite = true;
-    }
+/*
+plugins {
+    alias libs.plugins.guidesigner
+}
+*/
 
-    public IoRequest(int address, boolean isMemory, Consumer<Integer> callback) {
-        this.address = address;
-        this.isMemory = isMemory;
-        this.callback = callback;
-    }
+dependencies {
+    implementation libs.z80
 }
diff --git a/schemaParts/z80/src/java/lv/pko/KiCadLogicalSchemeSimulator/components/Z80/Z80Cpu.java b/schemaParts/z80/src/java/lv/pko/KiCadLogicalSchemeSimulator/components/Z80/Z80Cpu.java
@@ -30,18 +30,20 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 package lv.pko.KiCadLogicalSchemeSimulator.components.Z80;
+import com.codingrodent.microprocessor.Io.AsyncIoQueue;
+import com.codingrodent.microprocessor.Io.IoRequest;
+import com.codingrodent.microprocessor.Z80.CPUConstants;
+import com.codingrodent.microprocessor.Z80.Z80Core;
 import lv.pko.KiCadLogicalSchemeSimulator.api.pins.in.EdgeInPin;
 import lv.pko.KiCadLogicalSchemeSimulator.api.pins.in.InPin;
 import lv.pko.KiCadLogicalSchemeSimulator.api.pins.in.RisingEdgeInPin;
 import lv.pko.KiCadLogicalSchemeSimulator.api.pins.out.OutPin;
 import lv.pko.KiCadLogicalSchemeSimulator.api.pins.out.TriStateOutPin;
 import lv.pko.KiCadLogicalSchemeSimulator.api.schemaPart.SchemaPart;
-import lv.pko.KiCadLogicalSchemeSimulator.components.Z80.core.CPUConstants;
-import lv.pko.KiCadLogicalSchemeSimulator.components.Z80.core.IoRequest;
-import lv.pko.KiCadLogicalSchemeSimulator.components.Z80.core.Z80Core;
 
 public class Z80Cpu extends SchemaPart {
     private final Z80Core cpu;
+    private final AsyncIoQueue ioQueue = new AsyncIoQueue();
     protected InPin dIn;
     protected TriStateOutPin dOut;
     protected TriStateOutPin addOut;
@@ -67,12 +69,12 @@ public class Z80Cpu extends SchemaPart {
 
     public Z80Cpu(String id) {
         super(id, null);
-        cpu = new Z80Core();
+        cpu = new Z80Core(ioQueue);
         addInPin(new EdgeInPin("CLK", this) {
             @Override
             public void onFallingEdge() {
                 if (M > 0) {
-                    IoRequest ioRequest = cpu.ioQueue.peek();
+                    IoRequest ioRequest = ioQueue.requests.peek();
                     assert ioRequest != null;
                     if (T1) {
                         if (ioRequest.isMemory) {
@@ -121,9 +123,9 @@ public void onRisingEdge() {
                 if (M > 0) {
                     if (T4 || (!M1 && T3)) {
                         T = 1;
-                        cpu.ioQueue.poll();
+                        ioQueue.requests.poll();
 //                Log.trace(Z80Cpu.class, "cpuDone is {}", cpuDone);
-                        if (cpu.ioQueue.isEmpty()) {
+                        if (ioQueue.requests.isEmpty()) {
                             M = 1;
                         } else {
                             M++;
@@ -141,7 +143,7 @@ public void onRisingEdge() {
                     T4 = T == 4;
                     M1 = M == 1;
 //        Log.trace(Z80Cpu.class, "Set pins at {},{}", M, T);
-                    IoRequest ioRequest = cpu.ioQueue.peek();
+                    IoRequest ioRequest = ioQueue.requests.peek();
                     assert ioRequest != null;
                     if (T1) {
                         if (needRefreshPinReset) {
@@ -154,7 +156,7 @@ public void onRisingEdge() {
                         }
                         if (M1) {
                             cpu.executeOneInstruction();
-                            ioRequest = cpu.ioQueue.peek();
+                            ioRequest = ioQueue.requests.peek();
                             assert ioRequest != null;
                             m1Pin.setState(0);
                         }