this is the verilog-HDL implementation of MIPS32. the processor designed in single cycle mode.
Project has 2 part:
1. Processor:
The main verilog code of processor is in Modules.sv file.
2. Test program:
a simple test program designed. the binary instructions of test program are in instruction.txt. also the memory file of that program is in memory.txt. for case of knowing every binary instruction, we decode every instruction to its Assembly on Assembly to Bin.txt file.
below the RTL design of processpr, attached.
the controlling Signals(wire) state on each instruction:
the ALU function table:
