Here are
15 public repositories
matching this topic...
SDR-HLS is a Master Thesis focused on the implementation and optimization of Software-defined radio using Amaranth High Level Synthesis.
Updated
Jun 23, 2024
Verilog
My samples and tests on the FGPA ULX3S board and opensource toolchain for ECP5
Updated
Dec 31, 2020
Verilog
ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)
BNN-to-FPGA framework, written in VHDL and Python
Updated
Jul 16, 2021
Python
CLI-based HDL project management tool
Yet another faux-retro game system
Updated
Mar 3, 2024
Verilog
ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts
Updated
Oct 19, 2020
Shell
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
Updated
Nov 17, 2021
Verilog
Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
Updated
Nov 17, 2021
Verilog
AD/DA Converter Interface using ULX3S (primitive SDR)
Updated
Apr 12, 2019
Makefile
community projects that can be used with the ULX3S FPGA ESP32 board
Collection of various ulx3s examples
Updated
Oct 5, 2020
Python
FPGA ULX2/3 JTAG programmer
New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
Updated
Oct 16, 2023
GLSL
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