Hardware accelerator for Image processing in FPGA
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Updated
Oct 3, 2023 - C++
Hardware accelerator for Image processing in FPGA
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Mixing HLS and Backend Versions in Vitis
FPGA Acceleration for the LoFreq variant caller
DaCH: dataflow cache for high-level synthesis.
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