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Encryption/Decryption unit in FPGA written in VHDL with use of test benches and simulations

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
FinalVHDL.qar		FinalVHDL.qar
README.md		README.md
VHDL Ecryptor-Decryptor.mp4		VHDL Ecryptor-Decryptor.mp4
VHDL Encryptor-Decryptor.pdf		VHDL Encryptor-Decryptor.pdf

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VHDL_Encryptor_Decryptor

Encryption/Decryption unit in FPGA written in VHDL with use of test benches and simulations

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Encryption/Decryption unit in FPGA written in VHDL with use of test benches and simulations

fpga simulation vhdl altera modelsim testbench quartus de0

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