4-Bit-shift-register

4 Bit shift register created using Quartus prime and simulated using Modelsim.

RTL Viewer :-

Testbench waveform :-

Synthesis summary :-

See FPGA demonstration at

Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
output_files		output_files
simulation/modelsim		simulation/modelsim
.gitignore		.gitignore
4brsreg.mp4		4brsreg.mp4
README.md		README.md
RTL_gate_level.png		RTL_gate_level.png
Synthesis Summary.png		Synthesis Summary.png
Waveform.png		Waveform.png
b4sreg.qpf		b4sreg.qpf
b4sreg.qsf		b4sreg.qsf
b4sreg.sv		b4sreg.sv
b4sreg.sv.bak		b4sreg.sv.bak
b4sreg_nativelink_simulation.rpt		b4sreg_nativelink_simulation.rpt
b4sreg_tb.sv		b4sreg_tb.sv
b4sreg_tb.sv.bak		b4sreg_tb.sv.bak

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