CSE460 Lab Project

PROJECT TITLE: DESIGN 4-BIT ALU

Verilog HDL Code:

This repository contains the VERILOG HDL code for the Lab Project that I submitted for CSE460 Spring2023.

Group Information

• ATHAR NOOR MOHAMMAD RAFEE [20101396]
• A.S.M MAHABUB SIDDIQUI [20301040]
• AYON DAS [20301099]
• MD. SAKIB [20301180]
• MOHAMMED INZAM UL AZAM [20101144]

Project Report:

• The report was written in LaTeX and it's in a separate repository. Click to this link which will redirect you there.
• If you are looking for the PDF/Project Report then click here which will redirect you to the main.pdf file.

Issues

You've found a bug in the source code, a mistake in somewhere? You can help by submitting an issue on GitHub. Before you create an issue, make sure to search for the issue archive -- your issue may have already been addressed, and there maybe a temporary workaround!

Please try to create bug reports that are:

• Reproducible. include steps to reproduce the problem.
• Specific. include as much detail as possible: which version, what environment, etc.
• Unique. do not duplicate existing opened issues.
• Scoped to a single bug. one bug per report.