xilinx-sv

SystemVerilog component lib

TO DO

1. Add documentation for

   • axi checker
   • axi dump gen
   • axi memory writer
   • axi mm perf counter
   • axis uart bridge
   • axis fir filter

2. Fix issue with fir filter accumulator synthesizes to LUT&FF, but should in DSP

3. Add coefficients load interface for fir filter