ProyectoFinalCasiquenoEsteSi_nativelink_simulation.rpt

Info: Start Nativelink Simulation process
Info: NativeLink has detected VHDL design -- VHDL simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cycloneive
Quartus root          :  /home/ciro/intelFPGA_lite/17.0/quartus/linux64/
Quartus sim root      :  /home/ciro/intelFPGA_lite/17.0/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  vhdl
Version               :  93
Simulation Mode       :  GUI
Sim Output File       :  
Sim SDF file          :  
Sim dir               :  simulation/modelsim

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Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script /home/ciro/intelFPGA_lite/17.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File ProyectoFinalCasiquenoEsteSi_run_msim_rtl_vhdl.do already exists - backing up current file as ProyectoFinalCasiquenoEsteSi_run_msim_rtl_vhdl.do.bak11
Info: Spawning ModelSim-Altera Simulation software 
Info: NativeLink simulation flow was successful