Digital Design and Computer Architecture (DDCA), ETHZ

This Repository contains a summary of the DDCA course.

References

• Safari Research Group
• Course Website
• RISC-V CPU, my attempt at implementing a RISC-V CPU in Verilog

Summary

• DDCA

Verilog Examples

Some verilog examples are located in the directory verilog_examples. To run an example, change directory to the corresponding example and run make all to compile and execute the testbench. Then run make wave to view the generated waveform.

Make sure to have Icarus Verilog (iverilog, vvp) and GTKWave installed.

Labs

Some labs are located in the directory labs. To run, proceed the same way as for the verilog examples.