This project was developed as a work in the discipline of Digital Systems - UFMG - Department of Electronic Engineering.
This project has the proporse to simulate a real clock on Altera DE2 board, with a real time alarm, using VHDL language.
Apresentation link: https://prezi.com/view/mZ58moKQaPiSE2IHnEe4
Guilherme Amorim: [email protected]