GitHub - nickschiffer/cla_adder_7seg: 4bit_CLA_Adder

nickschiffer / cla_adder_7seg Public

4bit_CLA_Adder_7seg in Xilinx Vivado Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
cla_adder_7seg.hw		cla_adder_7seg.hw
cla_adder_7seg.ip_user_files		cla_adder_7seg.ip_user_files
cla_adder_7seg.runs		cla_adder_7seg.runs
cla_adder_7seg.sim/sim_1		cla_adder_7seg.sim/sim_1
cla_adder_7seg.srcs		cla_adder_7seg.srcs
cla_adder_7seg.xpr		cla_adder_7seg.xpr