SRAM Memory

A project to implement and test simple SRAM synchronous positive edge memory.

Design made using Verilog and Testbench made in 2 versions: System Verilog and Verilog.
Developed testcases to verify functioning of the design and used Questasim software for compilation and simulation. Test cases also includes frontdoor access and backdoor access along with random read write tests.

Files

Name		Name	Last commit message	Last commit date
Latest commit History 41 Commits
System Verilog		System Verilog
Verilog		Verilog
README.md		README.md

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