Add support for folding of OVM/UVM macros #164
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vhda
reviewed
Aug 12, 2018
| @@ -169,6 +169,12 @@ let g:verilog_syntax = { | |||
| \ 'highlight' : 'verilogStatement', | |||
| \ 'syn_argument': 'transparent keepend contains=ALLBUT,verilogInterface', | |||
| \ }], | |||
| \ 'ovm' : [{ | |||
| \ 'match_start' : '`\<\(ovm\|uvm\)_\a\+_utils_begin\>', | |||
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In hindsight that does seem a little simpler ;)
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Would you mind including a test case in |
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Don't you want to update, rebase on top of master and force push this branch? |
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Haven't forgotten this one, I just need to add the test case. I only haven't done that yet because I wanted to understand the test suite setup a little better before I started modfying it, and I also got massively sidetracked learning errorformat. :-) I have another minor PR (randsequence support) to submit which will also benefit from some added cases. |
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This commit adds a new folding option 'ovm' which will fold ovm/uvm macro constructs that have a begin/end
I originally wanted to name the new dictionary entry 'verif' since it encompasses both OVM and UVM, but for some reason the dictionary entry would not work when I named it either 'verif' or 'uvm'. But naming it 'ovm' does work. I can't explain that. 'ovm' isn't a terrible name but it's a deprecated library, so it's not ideal.
Let me know if you would like additions to the test cases to cover this change.