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Fix invalid references generated by VerilogMemDelays (backport #2588) #2599

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@mergify mergify bot commented Feb 3, 2023

This is an automatic backport of pull request #2588 done by Mergify.


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Transformation of mem readwriters whose address contain references to
readwriters of mems declared before it would contain invalid references
to untransformed memory readwriter, as the connection is not transformed.
This commit fixes this issue.

(cherry picked from commit 94d425f)
@mergify mergify bot added the Backport Automated backport, please consider for minor release label Feb 3, 2023
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